An RFIC (Radio Frequency Integrated Circuit) for use in communications is mounted with a Phase Locked Loop (PLL) circuit required for modulation and demodulation. The PLL circuit is mainly composed of a controlled oscillator, a frequency divider, a phase comparator, and a filter. The PLL circuit is a circuit which keeps an oscillation frequency constant by controlling a control voltage (or a digital code) to be supplied to the controlled oscillator, using a feedback loop. Since the oscillation frequency can be changed by changing a frequency division ratio of the frequency divider, the PLL circuit with the above configuration is also called a frequency synthesizer.
Specific configurations of the PLL circuit are described in, for example, a paper written by Robert Bogdan Staszewski et al. (“All-Digital PLL and Transmitter for Mobile Phones”, IEEE Journal of Solid-State Circuits, Vol. 40, No. 12, December 2005 (Non Patent Document 1)) and a paper written by Pin-En Su et al. (“Fractional-N Phase-Locked-Loop-Based Frequency Synthesis: A Tutorial”, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, Vol. 56, No. 12, December 2009 (Non Patent Document 2)). The former document discloses an All Digital PLL (ADPLL) circuit, and the latter document discloses a Fractional-N PLL synthesizer. In the Fractional-N PLL synthesizer, an oscillation frequency can be continuously changed by equivalently setting a frequency division number to a non-integer, using ΔΣ modulation.
Of the components constituting the PLL circuit, the controlled oscillator is described in, for example, Japanese Patent Laying-Open No. 3-196706 (Patent Document 1) and Japanese Patent Laying-Open No. 2007-74436 (Patent Document 2). In an oscillation circuit described in Japanese Patent Laying-Open No. 3-196706 (Patent Document 1), at least one of capacitive units determining an oscillation frequency includes a plurality of capacitors connected in parallel. By selecting one or more capacitors from the plurality of capacitors, a capacitance value of the capacitive unit is controlled, and thereby the oscillation frequency is controlled.
Japanese Patent Laying-Open No. 2007-74436 (Patent Document 2) discloses a configuration of a voltage-controlled oscillation circuit for obtaining a wideband oscillation frequency. Specifically, the voltage-controlled oscillation circuit in this document includes: a plurality of switched capacitors each having a MOS (Metal Oxide Semiconductor) switch and a fixed capacitor connected in series, the MOS switch being turned ON/OFF by a first external control signal; a variable capacitor capable of making a capacitor value variable by a second external control signal; an inductor; and semiconductor current control elements constituting a differential pair.
In a PLL circuit, a state having a constant oscillation frequency is called a “locked state”, and a state having an unstable oscillation frequency is called an “unlocked state”. For an RFIC for use in mobile communications for mobile phones and the like, specifications have been established on the frequency at which a mounted PLL circuit enters a locked state, and on the period of time taken from when the PLL circuit is unlocked to when the PLL circuit is relocked, and values thereof should fall within the ranges of the specifications.
For example, a technique described in Japanese Patent Laying-Open No. 2002-314408 (Patent Document 3) is intended to keep an oscillation frequency within the range of the specifications, by preventing overlapping of an unwanted frequency component on a locked output signal in a PLL circuit employing a fractional frequency division system.
Techniques described in Japanese Patent Laying-Open No. 2002-118461 (Patent Document 4) and Japanese Patent Laying-Open No. 2003-158452 (Patent Document 5) are intended to achieve a faster lock-up time. Specifically, a faster lock-up time is achieved by increasing the amount of current to be supplied to a charge pump circuit.
A technique described in Japanese Patent Laying-Open No. 2005-109608 (Patent Document 6) is also intended to achieve a faster lock-up time. Specifically, a lock-up time is controlled by making a cut-off frequency of a loop filter variable.
In mobile communications in which a plurality of terminals are connected to one base station (for example, WCDMA: Wideband Code Division Multiple Access), it is necessary to keep electric power from each terminal received by the base station constant by adjusting transmission power of each terminal in accordance with a distance between the base station and each terminal, in order to increase the number of terminals that can communicate at one time. At each terminal, transmission power is controlled by adjusting a gain of an amplifier at an output unit of an RFIC (for example, Kurt Hausmann and six others, “A SAW-less CMOS TX for EGPRS and WCDMA”, IEEE Radio Frequency Integrated Circuits Symposium, pp. 25 to 28, May 2010 (Non Patent Document 3)). As the distance between each terminal and the base station is decreased, power consumption in the RFIC is reduced (for a battery life measurement method, see, for example, GSM Association Official Document DG.09 v5.1 (Non Patent Document 4)).